This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-048249, filed Feb. 24, 2000, the entire contents of which are incorporated herein by reference.
The present invention relates to a negative-potential detecting circuit and a semiconductor memory device. More specifically, the present invention relates to a negative-potential detecting circuit for use in a power supply system of a semiconductor memory device.
A prior art negative-potential detecting circuit will now be described with reference to FIG. 1. As FIG. 1 shows, a negative-potential detecting circuit 10 includes resistance elements R10 and R11 and an operational amplifier OP10. One end of the resistance element R10 is connected to a VP power supply for applying a fixed positive potential VP to a semiconductor chip. One end of the resistance element R11 is connected to the other end of the resistance element R10, and the other end thereof is connected to a negative-potential power supply for generating a negative potential VBBO. The operational amplifier OP10 has an inverted input terminal (xe2x88x92) that receives a potential VO from a node between the resistance elements R10 and R11 and a non-inverted input terminal (+) that receives a reference potential Vref. The operational amplifier OP10 compares the reference potential Vref and the potential VO with each other and detects whether the negative potential VBBO reaches a desired level.
In the prior art negative-potential detecting circuit with the above arrangement, if the resistance elements R10 and R11 have their respective resistances r10 and r11, the potential VO applied to the operational amplifier OP10 is expressed by the following equation:
VO=VBBO+(r11/(r10+r11))xc2x7(VPxe2x88x92VBBO)
The resistances r10 and r11 are so determined that the potential VO becomes equal to the reference potential Vref when the negative potential VBBO reaches a desired potential VBB. Thus, the output SVBB of the operational amplifier OP100 is inverted when the negative potential VBBO reaches VBB. This inversion makes it possible to detect that the negative potential VBBO reaches the desired potential VBB.
However, the prior art negative-potential detecting circuit shown in FIG. 1 has the following problems:
(1) The precision in detecting the levels is obtained from r11/(r10+r11) of the above equation and it is not higher than 1. Since the potential VO depends on the potential-dividing ratio between the resistance elements R10 and R11, only part of the variation of the negative potential VBBO reflects the potential VO and the detection precision lowers.
(2) The use of the VP power supply increases the number of power supplies in the detecting circuit and thus complicates the circuit itself. Since the positive potential VP needs to be fixed, it is necessary to provide a VP power supply with a structure to charge an external power supply Vcc and keep it at a fixed potential, which complicates the detecting circuit. When a potential difference between VP and VBBO increases, it is likely to exceed the breakdown voltage of a diffusion layer constituting the resistance elements R10 and R11. For this reason, an intermediate potential between the positive and negative potentials VP and VBBO is applied forcibly to a well region surrounding the diffusion layer. A new power supply for applying the intermediate potential is required and the circuit arrangement is complicated accordingly.
(3) Since a transistor having a thick gate oxide and a high breakdown voltage is used in the detecting circuit, the detection sensitivity of the circuit lowers. This results from large variations of the potential VO with the negative potential VBBO. In some cases, the potential VO is set at a high potential close to the positive potential VP when the negative potential VBBO is at a GND level, and it is set at a negative potential lower than the reference potential Vref when the negative potential VBBO is at a highly negative potential. Thus, a transistor having a thick gate oxide and a high breakdown voltage should be used to constitute the operational amplifier OP10 such that it can cope with the case where the potential VO changes to a negative potential; accordingly, the detecting circuit decreases in detection sensitivity.
In order to resolve the above problems, a negative-potential detecting circuit is proposed in Mihara et al., xe2x80x9cA 29 mm2 1.8 V-only 16 Mb DINOR Flash Memory with Gate-Protected Poly-Diode (GPPD) Charge Pump,xe2x80x9d ISSCC 99 Digest of Technical Papers, February, 1999, pp 114-115. FIG. 2 illustrates a negative-potential detecting circuit 20 as proposed in Mihara et al.
The negative-potential detecting circuit 20 includes a PMOS transistor QP20, a resistance element R20, and an operational amplifier OP20. The PMOS transistor QP20 has a source connected to an external power supply Vcc. One end of the resistance element R20 is connected to the drain of the PMOS transistor QP20, and the other end thereof is connected to a negative-potential power supply for generating a negative potential VBBO. The operational amplifier OP20 has an inverted input terminal (xe2x88x92) that receives a potential VO from a node between the drain of the PMOS transistor QP20 and the resistance element R20 and a non-inverted input terminal (+) that receives a reference potential Vref. The circuit 20 also includes a PMOS transistor QP21, a resistance element R21, and an operational amplifier OP21. The PMOS transistor QP21 has a source connected to an external power supply Vcc. One end of the resistance element R21 is connected to the drain of the PMOS transistor QP21, and the other end thereof is grounded. The operational amplifier OP21 has an inverted input terminal (xe2x88x92) that receives a potential VO from a node between the drain of the PMOS transistor QP21 and the resistance element R21 and a non-inverted input terminal (+) that receives a reference potential Vref. The output terminal of the operational amplifier OP21 is connected to the gates of the PMOS transistors QP20 and QP21.
In the above negative-potential detecting circuit so arranged, the node between the PMOS transistor QP21 and the resistance element R21 is maintained at the reference potential Vref. The PMOS transistors QP21 and QP20 thus serve as a constant-current source 21 for supplying a constant current Ixe2x80x2 (=Vref/r21:r21 is a resistance of the resistance element R21). If a desired detection level of the negative potential VBBO is VBB, the resistance r20 of the resistance element R20 is expressed as follows: r20=(1 xe2x88x92VBB/Vref)xc2x7r21. Thus, the voltage VO at the node between the drain of the PMOS transistor QP20 and the resistance element R20 is given as follows: VO=VBBO+Vrefxe2x88x92VBB.
Assuming that the desired detection potential VBB is xe2x88x922.5 V and the reference potential Vref is 1.25V, xe2x88x92VBB/Vref is 2 and thus r20 becomes equal to 3r21. Considering a voltage drop in the resistance element R20, R20xc2x7Ixe2x80x2 is 1.25 V and thus 3r20 xc2x7Ixe2x80x2 becomes equal to 3.75V. If the potential VO=1.25V=Vref, the negative potential VBBO must be xe2x88x922.5 V that is equal to the desired detection potential VBB.
The above negative-potential detecting circuit of Mihara et al. has the following advantages over the circuit shown in FIG. 1:
(1) The precision of the detection level is 1 (=xcex94VO/xcex94VBBO). The precision is high because the potential VO is directly influenced by variations of the negative potential VBBO.
(2) Since no VP power supplies are required, the circuit arrangement can be simplified and the problem of a breakdown voltage of a diffusion layer constituting the resistance elements can be resolved.
The upper limit of the potential VO is Vcc. In some cases, however, the lower limit of the potential VO depends upon the negative potential VBBO and becomes very negative. A transistor having a thick gate oxide and a high breakdown voltage should be used to constitute the constant-current source 21 receiving the potential VO and the operational amplifier OP20. In this case, the sensitivity of detection may decrease.
A negative-potential detecting circuit according to an aspect of the present invention comprises:
a constant-current source;
a first resistance element having one end connected to an output node of the constant-current source and another end;
a second resistance element having one end connected to said another end of the first resistance element and another end connected to a negative-potential node whose potential is to be detected;
a first comparator having one input terminal connected to a connection node between the constant-current source and the first resistance element, another input terminal connected to a first reference potential node for setting a detection level of a potential of the negative-potential node, and an output terminal, which compares a potential of the connection node and a first reference potential of the first reference potential node with each other to determine a voltage level of the negative-potential node; and
a third resistance element having one end connected to a connection node of each of the first and second resistance elements and another end connected to a second reference potential node.
A semiconductor memory device according to an aspect of the present invention comprises:
a booster circuit which receives a power supply voltage from outside, generates a negative boost potential used for at least one of writing, reading, and erasing of stored data of a memory cell array in response to an internal control signal, and applies the negative boost potential to any one of a row decoder, a column decoder, and a source decoder; and
a control circuit which controls the negative boost potential applied to any one of the row decoder, the column decoder, and the source decoder from the booster circuit, the control circuit including a negative-potential detecting circuit,
wherein the negative-potential detecting circuit includes:
a constant-current source;
a first resistance element having one end connected to an output node of the constant-current source;
a second resistance element having one end connected to another end of the first resistance element and another end connected to a negative boost potential node whose potential is to be detected;
a comparator having one input terminal connected to a connection node between the constant-current source and the first resistance element and another input terminal connected to a first reference potential node setting a detection level of the negative boost potential, which compares a potential of the connection node and a first reference potential of the first reference potential node with each other to determine a voltage level of the negative boost potential node; and
a third resistance element having one end connected to a connection node of each of the first and second resistance elements and another end connected to a second reference potential node.
A negative-potential detecting circuit according to a second aspect of the present invention comprises:
a constant-current source;
a potential-dividing circuit provided between the constant-current source and a negative-potential node whose potential is to be detected, for dividing a potential difference between an output terminal of the constant-current source and the negative-potential node to generate a divided potential;
a comparator for comparing a potential of a detection node between the potential-dividing circuit and the constant-current source and a first reference potential for setting a detection level with each other to determine a level of a negative potential of the negative-potential node; and
a potential control circuit provided between an output node of the potential-dividing circuit for outputting the divided potential and a second reference potential, for when a potential of the negative-potential node varies, controlling a potential of the output node of the potential-dividing circuit to hold the potential of the detection node at a positive value.
A semiconductor memory device according to a third aspect of the present invention comprises:
a booster circuit which receives a power supply voltage from outside, for generating a negative boost potential used for at least one of writing, reading, and erasing of stored data of a memory cell array in response to an internal control signal, and applying the negative boost potential to any one of a row decoder, a column decoder, and a source decoder; and
a control circuit for controlling the negative boost potential applied to any one of the row decoder, the column decoder, and the source decoder from the booster circuit, the control circuit including a negative-potential detecting circuit,
wherein the negative-potential detecting circuit includes:
a constant-current source;
a first resistance element having one end connected to an output node of the constant-current source;
a second resistance element having one end connected to another end of the first resistance element and another end connected to a negative boost potential node whose potential is to be detected;
a comparator having one input terminal connected to a connection node between the constant-current source and the first resistance element and another input terminal connected to a first reference potential node for setting a detection level of the negative boost potential, for comparing a potential of the connection node and a first reference potential of the first reference potential node with each other to determine a voltage level of the negative boost potential node; and
a third resistance element having one end connected to a connection node of each of the first and second resistance elements and another end connected to a second reference potential node.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out hereinafter.